The present invention relates generally to the field of timing analysis for digital circuit design, and more particularly to statistical static timing analysis.
According to Wikipedia (http://en.wikipedia.org/wiki/Static_timing_analysis) as of Feb. 23, 2015: “Static timing analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation. . . . Gauging the ability of a circuit to operate at [a] specified speed requires an ability to measure, during the design process, [circuit] delay at numerous steps. . . . Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. . . . It has become a mainstay of design over the last few decades. . . . The time when a signal arrives can vary due to many reasons—the input data may vary, the circuit may perform different operations, the temperature and voltage may change, and there are manufacturing differences in the exact construction of each part. The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured.”
Further, according to Wikipedia (the above and http://en.wikipedia.org/wiki/Statistical_static_timing_analysis) as of Feb. 23, 2015: “Statistical static timing analysis (SSTA) is a procedure that is becoming increasingly necessary to handle the complexities of process and environmental variations in integrated circuits.” SSTA “replaces the normal deterministic timing of gates and interconnects [in STA] with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome. . . . [T]wo main categories of SSTA algorithms [are] path-based and block-based methods. A path-based algorithm sums gate and wire delays on specific paths. . . . A block-based algorithm generates the arrival times (and required) times for each node, working forward (and backward) from the clocked elements.”
The distributions of SSTA are typically represented in “canonical models,” or “canonical forms,” typically defined, at a high level, by the mean of the timing quantity being modeled summed with additional terms for that quantity's statistical sensitivities to various sources of variation. These terms may include linear terms, representing sensitivities based on only a single or first-order parameter, and/or cross-terms, representing sensitivities based on multiple or higher-order parameters. For example, a term for sensitivity due to silicon process, independent of other parameters, is a linear term, whereas a term for sensitivity due to silicon process with respect to OCV (on-chip-variation) is a cross-term. In this example, the cross-term is due to variation attributable to two parameters that exhibit interdependent variability, or “non-separability” (that is, where a sensitivity due to one parameter can be expressed as a non-constant function of some other parameter).